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Disambiguation of "Koyanagi, Mitsumasa"

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Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC.

, , , , , , , and . 3DIC, page TS8.26.1-TS8.26.4. IEEE, (2015)

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Other publications of authors with the same name

Stacked SOI pixel detector using versatile fine pitch μ-bump technology., , , , and . 3DIC, page 1-4. IEEE, (2011)High density Cu-TSVs and reliability issues., , , , and . 3DIC, page 1-4. IEEE, (2011)Future system-on-silicon LSI chips., , , , , and . IEEE Micro, 18 (4): 17-22 (1998)Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications., , , , , , , and . 3DIC, page 1-4. IEEE, (2021)Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding., , , , , and . 3DIC, page 1-4. IEEE, (2023)A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface., , , , , , , , , and 45 other author(s). ISSCC, page 422-424. IEEE, (2012)Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature., , , , , , and . 3DIC, page 1-5. IEEE, (2010)High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs., , , , , and . 3DIC, page 1-4. IEEE, (2011)3D memory chip stacking by multi-layer self-assembly technology., , , , , , , , and . 3DIC, page 1-4. IEEE, (2013)Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration., , , , , , , , , and . Micromachines, 2 (1): 49-68 (2011)