( en | de | ru )

 

Disambiguation of "Gaillardon, Pierre-Emmanuel"

Author of the publication

copydeleteadd this publication to your clipboard
Towards structured ASICs using polarity-tunable Si nanowire transistors.

, , , , , , and . DAC, page 123:1-123:4. ACM, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Pierre-Emmanuel Arduin

Pierre-Emmanuel Leni

Pierre Emmanuel Ilouga

Pierre-Emmanuel Cornilleau

Emmanuel Umana

 

Other publications of authors with the same name

Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors., and . VLSI-SoC, page 107-112. IEEE, (2018)GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment., , , , , , and . MICRO, page 334-346. ACM, (2019)A high-performance low-power near-Vt RRAM-based FPGA., , and . FPT, page 207-214. IEEE, (2014)Post-P&R Performance and Power Analysis for RRAM-Based FPGAs., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 639-650 (2018)Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)., , , , and . FPGA, page 262. ACM, (2015)A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors., , , and . VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 307-322. Springer, (2019)A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal., , , , and . CoRR, (2021)End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit., , , and . CoRR, (2022)Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (5): 2028-2036 (May 2023)Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (8): 1204-1213 (August 2023)