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An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform.

D. Wang, J. Shen, M. Wen, and C. Zhang. ICPP, page 98:1-98:10. ACM, (2019)

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Junzhong Liang

Wei Shen

Wan Shen

Hong Shen

Jian Shen

Other publications of authors with the same name

Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement.J. Shen, M. Wen, M. Tang, X. Zhao, and C. Zhang. FPGA, page 315. ACM, (2020)Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform.Q. Cheng, M. Wen, J. Shen, D. Wang, and C. Zhang. ICA3PP (1), volume 12452 of Lecture Notes in Computer Science, page 528-547. Springer, (2020)Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs.D. Wang, J. Shen, M. Wen, and C. Zhang. ISCAS, page 1-5. IEEE, (2019)S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness.Y. Li, M. Wen, R. Yang, J. Shen, Y. Cao, and J. Wang. ISCAS, page 2720-2724. IEEE, (2022)MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications.Y. Cao, M. Wen, J. Shen, S. Liu, Z. Wang, M. Tang, Y. Fang, J. Yang, R. Yang, Y. Kang and 1 other author(s). HPCC/DSS/SmartCity/DependSys, page 126-134. IEEE, (2022)Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA.T. Xiao, Y. Qiao, J. Shen, Q. Yang, and M. Wen. ICA3PP (1), volume 9528 of Lecture Notes in Computer Science, page 64-76. Springer, (2015)Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System.J. Shen, D. Wang, Y. Huang, M. Wen, and C. Zhang. DAC, page 207. ACM, (2019)Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs.J. Shen, Y. Qiao, Y. Huang, M. Wen, and C. Zhang. ISCAS, page 1-5. IEEE, (2018)MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-Core Processor.B. Sui, J. Shen, C. Sun, J. Wang, Z. Zheng, and W. Guo. DATE, page 1-6. IEEE, (2024)Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System.J. Shen, D. Wang, Y. Huang, M. Wen, and C. Zhang. FPGA, page 117. ACM, (2019)

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Disambiguation of "Shen, Junzhong"

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An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform.

Please choose a person to relate this publication to

Junzhong Liang

Wei Shen

Wan Shen

Hong Shen

Jian Shen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shen, Junzhong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform.

Please choose a person to relate this publication to

Junzhong Liang

Wei Shen

Wan Shen

Hong Shen

Jian Shen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform.