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Disambiguation of "Pawlowski, Robert"

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The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor.

, , , , , , , , , , , , , , , , , , , and . IEEE Micro, 43 (5): 78-87 (September 2023)

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Robert Pawlowski

Georg Pawlowski

Adam Pawlowski

Nina Pawlowski

Kai Pawlowski

 

Other publications of authors with the same name

Fast and Accurate Similarity Searching of Biopolymer Sequences with GPU and CUDA., , , and . ICA3PP (1), volume 7016 of Lecture Notes in Computer Science, page 230-243. Springer, (2011)Regaining throughput using completion detection for error-resilient, near-threshold logic., , and . DAC, page 974-979. ACM, (2012)Efficient Sparse Matrix-Vector Multiplication on Intel PIUMA Architecture., , , and . HPEC, page 1-2. IEEE, (2020)Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2014)PIUMA: Programmable Integrated Unified Memory Architecture., , , , , , , , , and 21 other author(s). CoRR, (2020)Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications., , , and . IEEE Comput. Archit. Lett., 9 (1): 21-24 (2010)The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor., , , , , , , , , and 10 other author(s). IEEE Micro, 43 (5): 78-87 (September 2023)Design automation methodology for improving the variability of synthesized digital circuits operating in the sub/near-threshold regime., , , , and . IGCC, page 1-6. IEEE Computer Society, (2011)A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI., , , , , , and . ISSCC, page 492-494. IEEE, (2012)