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(12)

• Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.
  Ashoka Visweswara Sathanur and Luca Benini and Alberto Macii and Enrico Macii and Massimo Poncino ISLPED 51-56 (2008)
  to dblp by dblp on 2008-08-18 00:00:00
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• Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
  Ashoka Visweswara Sathanur and Andrea Calimera and Luca Benini and Alberto Macii and Enrico Macii and Massimo Poncino DATE 1544-1549 (2007)
  to dblp by dblp on 2008-08-05 00:00:00
  | URL | BibTeX  
• Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.
  Karthik Duraisami and Prassanna Sithambaram and Ashoka Visweswara Sathanur and Alberto Macii and Enrico Macii and Massimo Poncino ISCAS 1061-1064 (2007)
  to dblp by dblp on 2008-08-05 00:00:00
  | URL | BibTeX  
• Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.
  Ashutosh Chakraborty and Karthik Duraisami and Ashoka Visweswara Sathanur and Prassanna Sithambaram and Alberto Macii and Enrico Macii and Massimo Poncino Integration 41 2-8 (2008)
  to dblp by dblp on 2008-08-05 00:00:00
  | URL | BibTeX  
• Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.
  Ashutosh Chakraborty and Karthik Duraisami and Ashoka Visweswara Sathanur and Prassanna Sithambaram and Alberto Macii and Enrico Macii and Massimo Poncino PATMOS 214-224 (2006)
  to dblp by dblp on 2008-05-13 00:00:00
  | URL | BibTeX  
• Dynamic thermal clock skew compensation using tunable delay buffers.
  Ashutosh Chakraborty and Karthik Duraisami and Ashoka Visweswara Sathanur and Prassanna Sithambaram and Luca Benini and Alberto Macii and Enrico Macii and Massimo Poncino ISLPED 162-167 (2006)
  to dblp by dblp on 2008-05-13 00:00:00
  | URL | BibTeX  
• Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.
  Ashutosh Chakraborty and Karthik Duraisami and Ashoka Visweswara Sathanur and Prassanna Sithambaram and Alberto Macii and Enrico Macii and Massimo Poncino ISCAS (2006)
  to dblp by dblp on 2008-05-13 00:00:00
  | URL | BibTeX  
• Optimal sleep transistor synthesis under timing and area constraints.
  Ashoka Visweswara Sathanur and Antonio Pullini and Luca Benini and Alberto Macii and Enrico Macii and Massimo Poncino ACM Great Lakes Symposium on VLSI 177-182 (2008)
  to dblp by dblp on 2008-05-13 00:00:00
  | URL | BibTeX  
• Timing-driven row-based power gating.
  Ashoka Visweswara Sathanur and Antonio Pullini and Luca Benini and Alberto Macii and Enrico Macii and Massimo Poncino ISLPED 104-109 (2007)
  to dblp by dblp on 2008-04-17 00:00:00
  | URL | BibTeX  
• Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach.
  Arun V. Sathanur and Ritochit Chakraborty and Vikram Jandhyala ICCAD 11-17 (2007)
  to dblp by dblp on 2007-12-31 00:00:00
  | URL | BibTeX