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Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.

K. Duraisami, P. Sithambaram, A. Sathanur, A. Macii, E. Macii, and M. Poncino. ISCAS, page 1061-1064. IEEE, (2007)

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Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, and M. Poncino. IEEE Trans. Very Large Scale Integr. Syst., 16 (6): 639-649 (2008)Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, and M. Poncino. Integr., 41 (1): 2-8 (2008)Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, and M. Poncino. PATMOS, volume 4148 of Lecture Notes in Computer Science, page 214-224. Springer, (2006)Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses.P. Sithambaram, A. Macii, and E. Macii. J. Embed. Comput., 3 (3): 155-165 (2009)Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs.P. Sithambaram, A. Macii, and E. Macii. PATMOS, volume 3728 of Lecture Notes in Computer Science, page 477-487. Springer, (2005)Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.A. Chakraborty, K. Duraisami, P. Sithambaram, A. Macii, E. Macii, and M. Poncino. IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (10): 2741-2752 (2010)Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.K. Duraisami, P. Sithambaram, A. Sathanur, A. Macii, E. Macii, and M. Poncino. ISCAS, page 1061-1064. IEEE, (2007)Dynamic thermal clock skew compensation using tunable delay buffers.A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, and M. Poncino. ISLPED, page 162-167. ACM, (2006)Thermal-Aware Design Techniques for Nanometer CMOS Circuits.A. Calimera, K. Duraisami, A. Sathanur, P. Sithambaram, R. Bahar, A. Macii, E. Macii, and M. Poncino. J. Low Power Electron., 4 (3): 374-384 (2008)Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, and M. Poncino. ISCAS, IEEE, (2006)

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Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.

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Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.