%0 Journal Article %1 journals/jssc/Briseno-Vidrios17 %A Briseno-Vidrios, Carlos %A Edward, Alexander %A Shafik, Ayman %A Palermo, Samuel %A Silva-Martínez, José %D 2017 %J IEEE J. Solid State Circuits %K dblp %N 3 %P 657-668 %T A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage. %U http://dblp.uni-trier.de/db/journals/jssc/jssc52.html#Briseno-Vidrios17 %V 52

@article{journals/jssc/Briseno-Vidrios17, added-at = {2020-08-30T00:00:00.000+0200}, author = {Briseno-Vidrios, Carlos and Edward, Alexander and Shafik, Ayman and Palermo, Samuel and Silva-Martínez, José}, biburl = {https://www.bibsonomy.org/bibtex/2aac61174fd689066ed1940270d37e6ab/dblp}, ee = {https://doi.org/10.1109/JSSC.2016.2634700}, interhash = {1c0bd30ebba42e8208e53b7d9de63b86}, intrahash = {aac61174fd689066ed1940270d37e6ab}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 3, pages = {657-668}, timestamp = {2020-08-31T11:43:34.000+0200}, title = {A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc52.html#Briseno-Vidrios17}, volume = 52, year = 2017 }