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Disambiguation of "Briseno-Vidrios, Carlos"

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A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage.

, , , , and . IEEE J. Solid State Circuits, 52 (3): 657-668 (2017)

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Benjamín Briseño

Benjamín Briseño

Cinthia Briseño Franke

Carlos Briede

Carlos Rodríguez

 

Other publications of authors with the same name

A 13bit 200MS/S pipeline ADC with current-mode MDACs., , , , , and . ISCAS, page 1-4. IEEE, (2017)A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique., , , , and . VLSIC, page 254-. IEEE, (2015)Low-Power Gm-C Filter Employing Current-Reuse Differential Difference Amplifiers., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (6): 635-639 (2017)A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 52 (2): 448-459 (2017)High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications., , , , and . MWSCAS, page 297-300. IEEE, (2017)A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer., , , and . IEEE J. Solid State Circuits, 51 (6): 1398-1409 (2016)A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage., , , , and . IEEE J. Solid State Circuits, 52 (3): 657-668 (2017)A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs., , , , , , , and . IEEE J. Solid State Circuits, 53 (11): 3280-3292 (2018)A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (9): 3373-3383 (2019)