%0 Conference Paper %1 conf/fpl/KanazawaM11 %A Kanazawa, Kenji %A Maruyama, Tsutomu %B FPL %D 2011 %I IEEE Computer Society %K dblp %P 38-43 %T An FPGA Solver for SAT-Encoded Formal Verification Problems. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#KanazawaM11 %@ 978-1-4577-1484-9

@inproceedings{conf/fpl/KanazawaM11, added-at = {2023-03-24T00:00:00.000+0100}, author = {Kanazawa, Kenji and Maruyama, Tsutomu}, biburl = {https://www.bibsonomy.org/bibtex/2d9cdc7e0b8b7f246c1a6341ee7a20c14/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2011}, ee = {https://doi.ieeecomputersociety.org/10.1109/FPL.2011.18}, interhash = {49660b5e2cbfacefe5d725cdaa3bef57}, intrahash = {d9cdc7e0b8b7f246c1a6341ee7a20c14}, isbn = {978-1-4577-1484-9}, keywords = {dblp}, pages = {38-43}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T14:51:39.000+0200}, title = {An FPGA Solver for SAT-Encoded Formal Verification Problems.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#KanazawaM11}, year = 2011 }