%0 Journal Article %1 journals/jssc/ElkholySSEH18 %A Elkholy, Ahmed %A Saxena, Saurabh %A Shu, Guanghua %A Elshazly, Amr %A Hanumolu, Pavan Kumar %D 2018 %J IEEE J. Solid State Circuits %K dblp %N 6 %P 1806-1817 %T Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. %U http://dblp.uni-trier.de/db/journals/jssc/jssc53.html#ElkholySSEH18 %V 53

@article{journals/jssc/ElkholySSEH18, added-at = {2020-08-30T00:00:00.000+0200}, author = {Elkholy, Ahmed and Saxena, Saurabh and Shu, Guanghua and Elshazly, Amr and Hanumolu, Pavan Kumar}, biburl = {https://www.bibsonomy.org/bibtex/29227451695c03156e08b31647a52acf8/dblp}, ee = {https://doi.org/10.1109/JSSC.2018.2817602}, interhash = {70d3892520f45ac623474a758cfe5719}, intrahash = {9227451695c03156e08b31647a52acf8}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 6, pages = {1806-1817}, timestamp = {2020-08-31T11:42:40.000+0200}, title = {Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc53.html#ElkholySSEH18}, volume = 53, year = 2018 }