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Disambiguation of "Elkholy, Ahmed"

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Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.

, , , , and . IEEE J. Solid State Circuits, 53 (6): 1806-1817 (2018)

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Hassan Elkholy

Shereen Elkholy

Mohamed Aly Elkholy

Ahmed Fattah Ahmed Ahmed

Yasar Luqman Ahmed

 

Other publications of authors with the same name

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS., , , , , , , , and . VLSIC, page 352-. IEEE, (2015)23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS., , , , , , , , , and . ISSCC, page 398-399. IEEE, (2016)A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC., , , , and . IEEE J. Solid State Circuits, 50 (4): 867-881 (2015)A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 53 (2): 445-457 (2018)Digital enhancement techniques for fractional-N frequency synthesizers. University of Illinois Urbana-Champaign, USA, (2016)8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS., , , , and . ISSCC, page 152-153. IEEE, (2017)A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS., , , , , and . ISSCC, page 392-394. IEEE, (2018)A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques., , , , and . IEEE J. Solid State Circuits, 55 (3): 592-601 (2020)A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links., , , , , and . IEEE J. Solid State Circuits, 50 (12): 3101-3119 (2015)A 3.2-GHz 405 fsrms Jitter -237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer., , , , , and . IEEE J. Solid State Circuits, 57 (3): 698-708 (2022)