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Disambiguation of "Hanumolu, Pavan Kumar"

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Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.

, , , , and . IEEE J. Solid State Circuits, 53 (6): 1806-1817 (2018)

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Pavan Kumar

Pavan Kumar

Pavan Kumar Penumakala

Pavan Kumar Pendli

Pavan Kumar Pamarthi

 

Other publications of authors with the same name

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS., , , , , , , , and . VLSIC, page 352-. IEEE, (2015)23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS., , , , , , , , , and . ISSCC, page 398-399. IEEE, (2016)A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity., , , and . VLSIC, page 188-189. IEEE, (2012)A low spur fractional-N frequency synthesizer architecture., , , and . ISCAS (3), page 2807-2810. IEEE, (2005)10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS., , , , and . ISSCC, page 182-183. IEEE, (2017)Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (11): 2880-2889 (2010)A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (3): 247-251 (2007)A Digital PLL With a Stochastic Time-to-Digital Converter., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1612-1621 (2009)A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery., , , , , and . IEEE J. Solid State Circuits, 46 (12): 3163-3173 (2011)A 0.016 mm2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS., , and . IEEE J. Solid State Circuits, 54 (8): 2186-2194 (2019)