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%0 Conference Paper
%1 conf/isqed/RosaSRR09
%A da Rosa Jr., Leomar S.
%A Schneider, Felipe Ribeiro
%A Ribas, Renato P.
%A Reis, André Inácio
%B ISQED
%D 2009
%I IEEE Computer Society
%K dblp
%P 324-329
%T Switch level optimization of digital CMOS gate networks.
%U http://dblp.uni-trier.de/db/conf/isqed/isqed2009.html#RosaSRR09
%@ 978-1-4244-2952-3
@inproceedings{conf/isqed/RosaSRR09,
added-at = {2023-03-23T00:00:00.000+0100},
author = {da Rosa Jr., Leomar S. and Schneider, Felipe Ribeiro and Ribas, Renato P. and Reis, André Inácio},
biburl = {https://www.bibsonomy.org/bibtex/2b6dde75cb4b6b2e70ff4a4cedd51951a/dblp},
booktitle = {ISQED},
crossref = {conf/isqed/2009},
ee = {https://doi.ieeecomputersociety.org/10.1109/ISQED.2009.4810315},
interhash = {a833f443b5369d56bcfdf04102086912},
intrahash = {b6dde75cb4b6b2e70ff4a4cedd51951a},
isbn = {978-1-4244-2952-3},
keywords = {dblp},
pages = {324-329},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T14:09:30.000+0200},
title = {Switch level optimization of digital CMOS gate networks.},
url = {http://dblp.uni-trier.de/db/conf/isqed/isqed2009.html#RosaSRR09},
year = 2009
}