( en | de | ru )

 

Disambiguation of "Ribas, Renato P."

Author of the publication

copydeleteadd this publication to your clipboard
Switch level optimization of digital CMOS gate networks.

, , , and . ISQED, page 324-329. IEEE Computer Society, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Maristella Ribas

Cesar Ribas Cezar

Renato Hasche

Renato Pasold

Renato Fassbind

 

Other publications of authors with the same name

A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design., , , and . ISPD, page 185-192. ACM, (2015)SwitchCraft: a framework for transistor network design., , , , , and . SBCCI, page 49-53. ACM, (2010)Performance evaluation of optimized transistor networks built using independent-gate FinFET., , , , and . LASCAS, page 227-230. IEEE, (2016)Concepção de Circuitos e Sistemas Integrados., , and . RITA, 8 (1): 7-21 (2001)A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 5126-5130 (2022)Parallel Combinational Equivalence Checking., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 3081-3092 (2020)Graph-Based Transistor Network Generation Method for Supergate Design., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC., , , and . IEEE Trans. Emerg. Top. Comput., 5 (2): 247-259 (2017)BTI and HCI first-order aging estimation for early use in standard cell technology mapping., , , and . Microelectron. Reliab., 53 (9-11): 1360-1364 (2013)ATMR design by construction based on two-level ALS., , , , and . SBCCI, page 1-6. IEEE, (2023)