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%0 Journal Article
%1 journals/vlsisp/SansaloniPTV07
%A Sansaloni, T.
%A Perez-Pascual, A.
%A Torres-Carot, Vicente
%A Valls, Javier
%D 2007
%J VLSI Signal Processing
%K dblp
%N 2
%P 183-187
%T Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.
%U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp47.html#SansaloniPTV07
%V 47
@article{journals/vlsisp/SansaloniPTV07,
added-at = {2019-09-25T00:00:00.000+0200},
author = {Sansaloni, T. and Perez-Pascual, A. and Torres-Carot, Vicente and Valls, Javier},
biburl = {https://www.bibsonomy.org/bibtex/2a0f3ee255bad13a76a392dc42f1c6d5b/dblp},
ee = {https://doi.org/10.1007/s11265-007-0055-8},
interhash = {dc19e562e7fe4cf5d0319bfab9fd69ce},
intrahash = {a0f3ee255bad13a76a392dc42f1c6d5b},
journal = {VLSI Signal Processing},
keywords = {dblp},
number = 2,
pages = {183-187},
timestamp = {2019-09-26T12:15:02.000+0200},
title = {Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.},
url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp47.html#SansaloniPTV07},
volume = 47,
year = 2007
}
