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Disambiguation of "Torres-Carot, Vicente"

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Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.

, , , and . VLSI Signal Processing, 47 (2): 183-187 (2007)

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Alexander Carôt

Isabel Anna Carota

Vicente Almazán

Vicente Jakas

Vicente Acuña

 

Other publications of authors with the same name

Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA., , , and . ICECS, page 408-411. IEEE, (2012)Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (7): 2150-2158 (2014)Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 102-111. Springer, (2002)Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems., , , , and . J. Signal Process. Syst., 56 (1): 35-40 (2009)FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques., , and . J. Syst. Archit., 56 (11): 588-596 (2010)DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems., , , , , , , , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 988-991. Springer, (2003)High-throughput FPGA-based emulator for structured LDPC codes., , , and . ICECS, page 404-407. IEEE, (2012)Design of high performance timing recovery loops for communication applications., , , and . SiPS, page 1-4. IEEE, (2006)Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method., , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (8): 501-505 (2012)Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications., , , and . J. Signal Process. Syst., 56 (1): 17-23 (2009)