%0 Journal Article %1 journals/jssc/PiloABBGHLRS12 %A Pilo, Harold %A Arsovski, Igor %A Batson, Kevin %A Braceras, Geordie %A Gabric, John A. %A Houle, Robert M. %A Lamphier, Steve %A Radens, Carl %A Seferagic, Adnan %D 2012 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 97-106 %T A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. %U http://dblp.uni-trier.de/db/journals/jssc/jssc47.html#PiloABBGHLRS12 %V 47

@article{journals/jssc/PiloABBGHLRS12, added-at = {2022-03-29T00:00:00.000+0200}, author = {Pilo, Harold and Arsovski, Igor and Batson, Kevin and Braceras, Geordie and Gabric, John A. and Houle, Robert M. and Lamphier, Steve and Radens, Carl and Seferagic, Adnan}, biburl = {https://www.bibsonomy.org/bibtex/2589244049555deda8732dd7c810344c3/dblp}, ee = {https://doi.org/10.1109/JSSC.2011.2164730}, interhash = {deabef2efaa02072fee1bd2c16411c21}, intrahash = {589244049555deda8732dd7c810344c3}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {97-106}, timestamp = {2024-04-08T10:44:19.000+0200}, title = {A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc47.html#PiloABBGHLRS12}, volume = 47, year = 2012 }