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Disambiguation of "Houle, Robert M."

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A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements.

, , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 97-106 (2012)

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Robert M Zoske

Robert M Stutz

Robert M Gillenkirch

Robert M Solomon

Robert M Fraunhoffer

 

Other publications of authors with the same name

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 97-106 (2012)1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%., , , , , , and . IEEE J. Solid State Circuits, 53 (1): 155-163 (2018)A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction., , , , , , , , , and 1 other author(s). ISSCC, page 322-323. IEEE, (2013)A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements., , , , , , , , , and 2 other author(s). ISSCC, page 254-256. IEEE, (2011)Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times.. IEEE J. Solid State Circuits, 43 (8): 1816-1825 (2008)Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set Times.. CICC, page 37-40. IEEE, (2007)Digital delay line clock shapers and multipliers., and . IBM J. Res. Dev., 39 (1-2): 93-104 (1995)12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%., , , , , , , , , and 3 other author(s). ISSCC, page 212-213. IEEE, (2017)