( en | de | ru )

 

Disambiguation of "Lamphier, Steve"

Author of the publication

copydeleteadd this publication to your clipboard
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements.

, , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 97-106 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Steve Völler

Steve Tonah

Steve Pasek

Steve Blechschmidt

Steve Klopfleisch

 

Other publications of authors with the same name

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management., , , , , and . ISSCC, page 378-379. IEEE, (2008)An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin., , , , , , , and . IEEE J. Solid State Circuits, 35 (11): 1641-1647 (2000)An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management., , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 155-162 (2009)Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond., , , , and . ITC, page 436-443. IEEE Computer Society, (2000)An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage., , , , , and . IEEE J. Solid State Circuits, 42 (4): 813-819 (2007)A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements., , , , , , , , , and 2 other author(s). ISSCC, page 254-256. IEEE, (2011)A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 97-106 (2012)A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface., , , , , , and . IEEE J. Solid State Circuits, 38 (11): 1974-1980 (2003)A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction., , , , , , , , , and 1 other author(s). ISSCC, page 322-323. IEEE, (2013)