%0 Conference Paper %1 conf/isvlsi/VijayakumarPK14 %A Vijayakumar, Arunkumar %A Patil, Vinay C. %A Kundu, Sandip %B ISVLSI %D 2014 %I IEEE Computer Society %K dblp %P 510-515 %T On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2014.html#VijayakumarPK14 %@ 978-1-4799-3763-9

@inproceedings{conf/isvlsi/VijayakumarPK14, added-at = {2023-03-24T00:00:00.000+0100}, author = {Vijayakumar, Arunkumar and Patil, Vinay C. and Kundu, Sandip}, biburl = {https://www.bibsonomy.org/bibtex/2c52a3ce65533e927b20d8b502ebecd52/dblp}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2014}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2014.76}, interhash = {50dc58f3ccaad3a4e8e95c449707f46b}, intrahash = {c52a3ce65533e927b20d8b502ebecd52}, isbn = {978-1-4799-3763-9}, keywords = {dblp}, pages = {510-515}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T11:07:29.000+0200}, title = {On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2014.html#VijayakumarPK14}, year = 2014 }