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On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery.

, , and . ISVLSI, page 510-515. IEEE Computer Society, (2014)

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On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery., , and . ISVLSI, page 510-515. IEEE Computer Society, (2014)A Chaotic Ring oscillator based Random Number Generator., , and . HOST, page 160-165. IEEE Computer Society, (2014)Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits., , , and . ACM Great Lakes Symposium on VLSI, page 265-270. ACM, (2011)Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques., , , , and . CoRR, (2019)An Efficient Method for Clock Skew Scheduling to Reduce Peak Current., , and . VLSID, page 505-510. IEEE Computer Society, (2016)On meta-obfuscation of physical layouts to conceal design characteristics., , and . DFT, page 147-152. IEEE Computer Society, (2016)On pattern generation for maximizing IR drop., , , and . ISQED, page 731-737. IEEE, (2014)On testing physically unclonable functions for uniqueness., , and . ISQED, page 368-373. IEEE, (2016)On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors., , and . ISVLSI, page 120-125. IEEE Computer Society, (2012)Machine learning resistant strong PUF: Possible or a pipe dream?, , , and . HOST, page 19-24. IEEE Computer Society, (2016)