%0 Conference Paper %1 conf/vlsid/WangMG09 %A Wang, Weixun %A Mishra, Prabhat %A Gordon-Ross, Ann %B VLSI Design %D 2009 %I IEEE Computer Society %K dblp %P 547-552 %T SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2009.html#WangMG09 %@ 978-0-7695-3506-7

@inproceedings{conf/vlsid/WangMG09, added-at = {2024-05-07T00:00:00.000+0200}, author = {Wang, Weixun and Mishra, Prabhat and Gordon-Ross, Ann}, biburl = {https://www.bibsonomy.org/bibtex/2d293bb1e7a2a9909a68bc0071bf9f25c/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2009}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2009.66}, interhash = {897a69c544425d68116a969ec37aafa6}, intrahash = {d293bb1e7a2a9909a68bc0071bf9f25c}, isbn = {978-0-7695-3506-7}, keywords = {dblp}, pages = {547-552}, publisher = {IEEE Computer Society}, timestamp = {2024-05-13T08:18:02.000+0200}, title = {SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2009.html#WangMG09}, year = 2009 }