Author of the publication

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems.

, , and . VLSI Design, page 547-552. IEEE Computer Society, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Scalable Test Generation for Trojan Detection Using Side Channel Analysis., , and . IEEE Trans. Inf. Forensics Secur., 13 (11): 2746-2760 (2018)Lightweight Anonymous Routing in NoC based SoCs., , and . DATE, page 334-337. IEEE, (2020)Processor-memory coexploration using an architecture description language., , and . ACM Trans. Embed. Comput. Syst., 3 (1): 140-162 (2004)Automatic RTL Test Generation from SystemC TLM Specifications., , and . ACM Trans. Embed. Comput. Syst., 11 (2): 38:1-38:25 (2012)Dynamic Cache Reconfiguration for Soft Real-Time Systems., , and . ACM Trans. Embed. Comput. Syst., 11 (2): 28:1-28:31 (2012)MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection., , and . ACM Conference on Computer and Communications Security, page 130-141. ACM, (2016)Efficient trace signal selection using augmentation and ILP techniques., , and . ISQED, page 148-155. IEEE, (2014)Efficient Test Generation for Trojan Detection using Side Channel Analysis., and . DATE, page 408-413. IEEE, (2019)PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme., and . DAC, page 705-710. ACM, (2010)Decoding-Aware Compression of FPGA Bitstreams., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (3): 411-419 (2011)