%0 Journal Article %1 journals/jssc/ChunMRA22 %A Chun, Yusang %A Megahed, Mohamed %A Ramachandran, Ashwin %A Anand, Tejasvi %D 2022 %J IEEE J. Solid State Circuits %K dblp %N 5 %P 1527-1541 %T A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc57.html#ChunMRA22 %V 57

@article{journals/jssc/ChunMRA22, added-at = {2022-05-18T00:00:00.000+0200}, author = {Chun, Yusang and Megahed, Mohamed and Ramachandran, Ashwin and Anand, Tejasvi}, biburl = {https://www.bibsonomy.org/bibtex/2ec0dfa5cf337123b977d634e98421c3c/dblp}, ee = {https://doi.org/10.1109/JSSC.2022.3146097}, interhash = {105ca3c0e3a38f22255019301c6ec8a9}, intrahash = {ec0dfa5cf337123b977d634e98421c3c}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 5, pages = {1527-1541}, timestamp = {2024-04-08T10:43:58.000+0200}, title = {A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc57.html#ChunMRA22}, volume = 57, year = 2022 }