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Disambiguation of "Megahed, Mohamed"

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A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS.

, , , and . IEEE J. Solid State Circuits, 57 (5): 1527-1541 (2022)

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Mosaad Megahed

Mustafa Megahed

Waleed Megahed

Khaled Megahed

Aly Megahed

 

Other publications of authors with the same name

An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS., , , and . IEEE J. Solid State Circuits, 55 (7): 1946-1959 (2020)Weight Prediction Using the Hybrid Stacked-LSTM Food Selection Model., , , , , and . Comput. Syst. Sci. Eng., 46 (1): 765-781 (2023)A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit., , , and . VLSI Circuits, page 1-2. IEEE, (2021)FA*IR: A Fair Top-k Ranking Algorithm., , , , , and . CIKM, page 1569-1578. ACM, (2017)12-Gb/s low-power voltage-mode driver for multi-standard serial-link applications., , , and . ICECS, page 101-104. IEEE, (2016)A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm., , and . CICC, page 1-4. IEEE, (2019)A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (12): 4876-4887 (2019)A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS., and . IEEE J. Solid State Circuits, 58 (5): 1386-1399 (May 2023)A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS., , , and . IEEE J. Solid State Circuits, 57 (5): 1527-1541 (2022)A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail., , and . VLSI Technology and Circuits, page 188-189. IEEE, (2022)