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Disambiguation of "Chun, Yusang"

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A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS.

, , , and . IEEE J. Solid State Circuits, 57 (5): 1527-1541 (2022)

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Dai-Hai Chung

Hae-Bon Chung

Chong-Woon Chung

Myeong-Kee Chung

Ki-Nam Chung

 

Other publications of authors with the same name

A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET., , , , , , , , , and 11 other author(s). ISSCC, page 110-111. IEEE, (2023)An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS., , , and . IEEE J. Solid State Circuits, 55 (7): 1946-1959 (2020)A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS., , and . ESSCIRC, page 269-272. IEEE, (2019)A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit., , , and . VLSI Circuits, page 1-2. IEEE, (2021)A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS., and . CICC, page 1-4. IEEE, (2019)A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS., , , and . IEEE J. Solid State Circuits, 57 (5): 1527-1541 (2022)A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8., , , and . VLSI Circuits, page 1-2. IEEE, (2021)