%0 Conference Paper %1 conf/essderc/BaoYRCBVBCRDRMTVTW14 %A Bao, Trong Huynh %A Yakimets, Dmitry %A Ryckaert, Julien %A Ciofi, Ivan %A Baert, Rogier %A Veloso, Anabela %A Bömmels, Jürgen %A Collaert, Nadine %A Roussel, Philippe %A Demuynck, S. %A Raghavan, Praveen %A Mercha, Abdelkarim %A Tokei, Zsolt %A Verkest, Diederik %A Thean, Aaron %A Wambacq, Piet %B ESSDERC %D 2014 %I IEEE %K dblp %P 102-105 %T Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. %U http://dblp.uni-trier.de/db/conf/essderc/essderc2014.html#BaoYRCBVBCRDRMTVTW14 %@ 978-1-4799-4378-4

@inproceedings{conf/essderc/BaoYRCBVBCRDRMTVTW14, added-at = {2019-05-24T00:00:00.000+0200}, author = {Bao, Trong Huynh and Yakimets, Dmitry and Ryckaert, Julien and Ciofi, Ivan and Baert, Rogier and Veloso, Anabela and Bömmels, Jürgen and Collaert, Nadine and Roussel, Philippe and Demuynck, S. and Raghavan, Praveen and Mercha, Abdelkarim and Tokei, Zsolt and Verkest, Diederik and Thean, Aaron and Wambacq, Piet}, biburl = {https://www.bibsonomy.org/bibtex/2f85bec18a91f06ff6605f3d7c7e02c71/dblp}, booktitle = {ESSDERC}, crossref = {conf/essderc/2014}, ee = {https://doi.org/10.1109/ESSDERC.2014.6948768}, interhash = {c7f8993d2d11da03ee060e1690b4ab64}, intrahash = {f85bec18a91f06ff6605f3d7c7e02c71}, isbn = {978-1-4799-4378-4}, keywords = {dblp}, pages = {102-105}, publisher = {IEEE}, timestamp = {2019-10-17T12:39:26.000+0200}, title = {Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.}, url = {http://dblp.uni-trier.de/db/conf/essderc/essderc2014.html#BaoYRCBVBCRDRMTVTW14}, year = 2014 }