3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.
@inproceedings{conf/isscc/KawamotoNKYNTUH15,
added-at = {2015-03-24T00:00:00.000+0100},
author = {Kawamoto, Takashi and Norimatsu, Takayasu and Kogo, Kenji and Yuki, Fumio and Nakajima, Norio and Tsuge, Masatoshi and Usugi, Tatsunori and Hokari, Tomofumi and Koba, Hideki and Komori, Takemasa and Nasu, Junya and Kawamata, Tsuneo and Ito, Yuichi and Umai, Seiichi and Kumazawa, Jun and Kurahashi, Hiroaki and Muto, Takashi and Yamashita, Takeo and Hasegawa, Masatoshi and Higeta, Keiichi},
biburl = {https://www.bibsonomy.org/bibtex/2f46d2d73809c64994d81419649655a6b/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2015},
ee = {http://dx.doi.org/10.1109/ISSCC.2015.7062922},
interhash = {501bbe0cea76c0a9807930d28fa9857d},
intrahash = {f46d2d73809c64994d81419649655a6b},
isbn = {978-1-4799-6224-2},
keywords = {dblp},
pages = {1-3},
publisher = {IEEE},
timestamp = {2015-06-18T16:09:38.000+0200},
title = {3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2015.html#KawamotoNKYNTUH15},
year = 2015
}