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Disambiguation of "Muto, Takashi"

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3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.

, , , , , , , , , , , , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Takashi Seki

Shuhei Muto

Clément Mutombo

Takashi Iwata

Takashi Numaguchi

 

Other publications of authors with the same name

6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiers., , , , , , , , , and 1 other author(s). ISSCC, page 116-117. IEEE, (2016)A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 46 (12): 3101-3112 (2011)3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS., , , , , , , , , and 10 other author(s). ISSCC, page 1-3. IEEE, (2015)3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS., , , , , , , , , and 9 other author(s). ISSCC, page 60-61. IEEE, (2016)A 1.8e-rms Temporal Noise Over 110-dB-Dynamic Range 3.4µm Pixel Pitch Global-Shutter CMOS Image Sensor With Dual-Gain Amplifiers SS-ADC, Light Guide Structure, and Multiple-Accumulation Shutter., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 53 (1): 219-228 (2018)110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock., , , , , , , , and . IEEE J. Solid State Circuits, 34 (11): 1526-1533 (1999)10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link., , , , , , , , , and 5 other author(s). ISSCC, page 148-150. IEEE, (2011)