%0 Conference Paper %1 conf/ismvl/NagaiOH08 %A Nagai, Tasuku %A Onizawa, Naoya %A Hanyu, Takahiro %B ISMVL %D 2008 %I IEEE Computer Society %K dblp %P 70-75 %T High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. %U http://dblp.uni-trier.de/db/conf/ismvl/ismvl2008.html#NagaiOH08 %@ 978-0-7695-3155-7

@inproceedings{conf/ismvl/NagaiOH08, added-at = {2023-03-23T00:00:00.000+0100}, author = {Nagai, Tasuku and Onizawa, Naoya and Hanyu, Takahiro}, biburl = {https://www.bibsonomy.org/bibtex/25d1f1b584f120f19414585ffb25d54ab/dblp}, booktitle = {ISMVL}, crossref = {conf/ismvl/2008}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISMVL.2008.12}, interhash = {564dbccb57241aea96e7357f7fcc679b}, intrahash = {5d1f1b584f120f19414585ffb25d54ab}, isbn = {978-0-7695-3155-7}, keywords = {dblp}, pages = {70-75}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T17:18:04.000+0200}, title = {High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.}, url = {http://dblp.uni-trier.de/db/conf/ismvl/ismvl2008.html#NagaiOH08}, year = 2008 }