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Disambiguation of "Onizawa, Naoya"

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High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.

, , and . ISMVL, page 70-75. IEEE Computer Society, (2008)

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Naoya Koseki

 

Other publications of authors with the same name

High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip., and . ISCAS, page 157-160. IEEE, (2010)Stochastic Implementation of Simulated Quantum Annealing on PYNQ., , , and . ICFPT, page 274-275. IEEE, (2023)Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors., , and . ISMVL, page 109-114. IEEE Computer Society, (2015)Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating., , , and . ISMVL, page 254-259. IEEE Computer Society, (2013)Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders., , and . ISMVL, page 138-143. IEEE Computer Society, (2005)High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians., and . ISCAS, page 1-5. IEEE, (2021)VLSI implementation of deep neural networks using integral stochastic computing., , , , and . ISTC, page 216-220. IEEE, (2016)Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop., , , and . NEWCAS, page 1-4. IEEE, (2015)Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge., , and . ICECS, page 434-437. IEEE, (2019)FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic., , and . ICECS, page 115-116. IEEE, (2019)