%0 Journal Article %1 journals/tcad/PullelaMP96 %A Pullela, Satyamurthy %A Menezes, Noel %A Pileggi, Lawrence T. %D 1996 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 6 %P 691-701 %T Post-processing of clock trees via wiresizing and buffering for robust design. %U http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#PullelaMP96 %V 15

@article{journals/tcad/PullelaMP96, added-at = {2020-09-24T00:00:00.000+0200}, author = {Pullela, Satyamurthy and Menezes, Noel and Pileggi, Lawrence T.}, biburl = {https://www.bibsonomy.org/bibtex/24f72bd0b9b1eefeaf0d0640bcd53b996/dblp}, ee = {https://doi.org/10.1109/43.503938}, interhash = {5d858a638336ca36caac0714be233edf}, intrahash = {4f72bd0b9b1eefeaf0d0640bcd53b996}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 6, pages = {691-701}, timestamp = {2020-09-25T11:50:48.000+0200}, title = {Post-processing of clock trees via wiresizing and buffering for robust design.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#PullelaMP96}, volume = 15, year = 1996 }