A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.
@inproceedings{conf/isscc/NomuraTFTUYMKHYTUTMKSHMSWHT08,
added-at = {2017-03-30T00:00:00.000+0200},
author = {Nomura, Shuou and Tachibana, Fumihiko and Fujita, Tetsuya and Teh, Chen Kong and Usui, Hiroyuki and Yamane, Fumiyuki and Miyamoto, Yukimasa and Kumtornkittikul, Chaiyasit and Hara, Hiroyuki and Yamashita, Takahiro and Tanabe, Jun and Uchiyama, Masaru and Tsuboi, Yoshiro and Miyamori, Takashi and Kitahara, Takeshi and Sato, Hironori and Homma, Y. and Matsumoto, Shuuji and Seki, Keiko and Watanabe, Y. and Hamada, Mototsugu and Takahashi, Makoto},
biburl = {https://www.bibsonomy.org/bibtex/2808dcab9e152451a2a5a48f71a8daf1e/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2008},
ee = {http://dx.doi.org/10.1109/ISSCC.2008.4523157},
interhash = {5e008c4e97b592acfff39674cb6940a6},
intrahash = {808dcab9e152451a2a5a48f71a8daf1e},
isbn = {978-1-4244-2010-0},
keywords = {dblp},
pages = {262-263},
publisher = {IEEE},
timestamp = {2017-03-31T11:39:05.000+0200},
title = {A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2008.html#NomuraTFTUYMKHYTUTMKSHMSWHT08},
year = 2008
}