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A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.

S. Nomura, F. Tachibana, T. Fujita, C. Teh, H. Usui, F. Yamane, Y. Miyamoto, C. Kumtornkittikul, H. Hara, T. Yamashita, J. Tanabe, M. Uchiyama, Y. Tsuboi, T. Miyamori, T. Kitahara, H. Sato, Y. Homma, S. Matsumoto, K. Seki, Y. Watanabe, M. Hamada, and M. Takahashi. ISSCC, page 262-263. IEEE, (2008)

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Sandra Hamada

Taha Auf Hamada

Mahmoud Ahmed Hamada

Azhari Abdelazim Hamada

Hamada Dahy Hussein Mahboub

Other publications of authors with the same name

Wireless power transfer to stacked modules for IoT sensor nodes.S. Yanagawa, R. Shimizu, M. Hamada, T. Shimizu, and T. Kuroda. ISOCC, page 59-60. IEEE, (2017)A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier.S. Kousai, D. Miyashita, J. Wadatsumi, A. Maki, T. Sekiguchi, R. Ito, and M. Hamada. ISSCC, page 214-215. IEEE, (2008)A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS.J. Deguchi, D. Miyashita, Y. Ogasawara, G. Takemura, M. Iwanaga, K. Sami, R. Ito, J. Wadatsumi, Y. Tsuda, S. Oda and 3 other author(s). ISSCC, page 456-457. IEEE, (2010)A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network.Y. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada, and T. Kuroda. ASP-DAC, page 182-183. ACM, (2023)A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS.K. Shiba, T. Omori, M. Hamada, and T. Kuroda. ASP-DAC, page 97-98. ACM, (2021)A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation.R. Miura, S. Shibata, M. Usui, A. Kosuge, M. Hamada, and T. Kuroda. ASP-DAC, page 5-6. IEEE, (2022)A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI.M. Hamada, H. Hara, T. Fujita, C. Teh, T. Shimazawa, N. Kawabe, T. Kitahara, Y. Kikuchi, T. Nishikawa, M. Takahashi and 1 other author(s). CICC, page 527-530. IEEE, (2005)A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network.D. Li, Y. Hsu, R. Sumikawa, A. Kosuge, M. Hamada, and T. Kuroda. ISCAS, page 1-5. IEEE, (2023)A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes.K. Shiba, T. Omori, K. Ueyoshi, K. Ando, K. Hirose, S. Takamaeda-Yamazaki, M. Motomura, M. Hamada, and T. Kuroda. ISCAS, page 1-5. IEEE, (2020)A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver.K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda. IEEE J. Solid State Circuits, 58 (7): 2075-2086 (2023)

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Disambiguation of "Hamada, Mototsugu"