%0 Conference Paper %1 conf/asscc/ChaeHPKKSCJK15 %A Chae, Joo-Hyung %A Hong, Gi-Moon %A Park, Jihwan %A Kim, Mino %A Ko, Hyeongjun %A Shin, Woo-Yeol %A Chi, Hankyu %A Jeong, Deog-Kyoon %A Kim, Suhwan %B A-SSCC %D 2015 %I IEEE %K dblp %P 1-4 %T A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. %U http://dblp.uni-trier.de/db/conf/asscc/asscc2015.html#ChaeHPKKSCJK15 %@ 978-1-4673-7191-9

@inproceedings{conf/asscc/ChaeHPKKSCJK15, added-at = {2020-06-15T00:00:00.000+0200}, author = {Chae, Joo-Hyung and Hong, Gi-Moon and Park, Jihwan and Kim, Mino and Ko, Hyeongjun and Shin, Woo-Yeol and Chi, Hankyu and Jeong, Deog-Kyoon and Kim, Suhwan}, biburl = {https://www.bibsonomy.org/bibtex/28e3b400f6074986ebe4f9678bdbe76d4/dblp}, booktitle = {A-SSCC}, crossref = {conf/asscc/2015}, ee = {https://doi.org/10.1109/ASSCC.2015.7387434}, interhash = {7bbd0c46f56598f0f2fd980c387c86df}, intrahash = {8e3b400f6074986ebe4f9678bdbe76d4}, isbn = {978-1-4673-7191-9}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2020-06-16T13:06:56.000+0200}, title = {A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.}, url = {http://dblp.uni-trier.de/db/conf/asscc/asscc2015.html#ChaeHPKKSCJK15}, year = 2015 }