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Disambiguation of "Jeong, Deog-Kyoon"

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A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.

, , , , , , , , and . A-SSCC, page 1-4. IEEE, (2015)

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Su-Jeong Jeong

Wonrae Jeong

Hang-Kyun Jeong

Hyung-Gon Jeong

Chang-Kyo Jeong

 

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A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS., , and . ISCAS, page 1869-1872. IEEE, (2014)A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology., and . ISOCC, page 53-56. IEEE, (2012)A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range., , , , , and . ISSCC, page 250-251. IEEE, (2013)A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b., , , , , , , , , and 1 other author(s). ESSCIRC, page 225-228. IEEE, (2003)0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link., , , , , and . VLSI Technology and Circuits, page 30-31. IEEE, (2022)A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS., , , , , , and . ISSCC, page 410-411. IEEE, (2023)A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µm., , , , and . ISSCC, page 2402-2411. IEEE, (2006)A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration., , , , , and . ISSCC, page 1-3. IEEE, (2022)A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 Receiver., , , and . ISOCC, page 379-380. IEEE, (2021)A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS., , , , , , and . ISOCC, page 127-128. IEEE, (2021)