%0 Journal Article %1 journals/tc/ParkDS04 %A Park, Joonseok %A Diniz, Pedro C. %A Shayee, K. R. Shesha %D 2004 %J IEEE Trans. Computers %K dblp %N 11 %P 1420-1435 %T Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. %U http://dblp.uni-trier.de/db/journals/tc/tc53.html#ParkDS04 %V 53

@article{journals/tc/ParkDS04, added-at = {2020-06-15T00:00:00.000+0200}, author = {Park, Joonseok and Diniz, Pedro C. and Shayee, K. R. Shesha}, biburl = {https://www.bibsonomy.org/bibtex/23c368a5abe873461504a561f14fb533e/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TC.2004.101}, interhash = {af6e62f63213c8980be2c26281042714}, intrahash = {3c368a5abe873461504a561f14fb533e}, journal = {IEEE Trans. Computers}, keywords = {dblp}, number = 11, pages = {1420-1435}, timestamp = {2020-06-16T11:51:51.000+0200}, title = {Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations.}, url = {http://dblp.uni-trier.de/db/journals/tc/tc53.html#ParkDS04}, volume = 53, year = 2004 }