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Disambiguation of "Raghunathan, Anand"

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Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.

, , and . DAC, page 883-886. IEEE, (2007)

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Davinder Kumar Anand

Raghunathan Ramakrishnan

Devanathan Raghunathan

Amar Frank Anand

Madhankumar Anandhakrishnan

 

Other publications of authors with the same name

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips., , , and . DAC, page 513-518. ACM, (2000)Hardware Accelerated Power Estimation, , and . CoRR, (2007)STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks., , , and . CoRR, (2014)System-on-Chip Power Management Considering Leakage Power Variations., , , and . DAC, page 877-882. IEEE, (2007)Analyzing the energy consumption of security protocols., , , and . ISLPED, page 30-35. ACM, (2003)Emulation-Based Analysis of System-on-Chip Performance Under Variations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3401-3414 (2016)Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (3): 296-308 (2007)Variation-Aware System-Level Power Analysis., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1173-1184 (2010)High-level macro-modeling and estimation techniques for switching activity and power consumption., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (4): 538-557 (2003)Application-specific heterogeneous multiprocessor synthesis using extensible processors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1589-1602 (2006)