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Disambiguation of "Zaruba, Florian"

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The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance.

, , , and . ICECS, page 767-770. IEEE, (2019)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hans Zaruba

Marc-Michael Zaruba

Florian Klasovsky

Syntheseparameter-Reaktivitätsbeziehungen für neue Palladiumoxidkatalysatoren in feinchemischen Hydrierungen. TU Darmstadt, (2009)

Florian Franz

Realzeittest von Fahrzeugsoftware-Komponenten. TU München, (2009)

Florian Beißner

Funktionelle Bildgebung des vegetativen Nervensystems: neue Ansätze zur fMRT-Messung des menschlichen Hirnstamms. Uni Frankfurt Main, (2010)
 

Other publications of authors with the same name

Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (2): 530-543 (2020)FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing., , , and . CoRR, (2020)Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI., , , , and . CoRR, (2019)A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing., , and . Hot Chips Symposium, page 1-24. IEEE, (2020)Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores., , , and . IEEE Trans. Computers, 70 (2): 212-227 (2021)Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores., , , , , and . ISCAS, page 1-5. IEEE, (2021)FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (4): 774-787 (2021)An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication., , , , , , and . IEEE Trans. Computers, 71 (8): 1794-1809 (2022)Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra., , , , and . CoRR, (2023)An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication., , , , , , and . CoRR, (2020)