( en | de | ru )

 

Disambiguation of "Kameyama, Michitaka"

Author of the publication

copydeleteadd this publication to your clipboard
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates.

, , and . IEICE Trans. Electron., 89-C (11): 1655-1661 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Michitaka Ota

Shin'ichi Kameyama

 

Other publications of authors with the same name

A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment., and . APCCAS, page 1803-1806. IEEE, (2006)An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture., , , and . ASP-DAC, page 89-90. IEEE, (2011)Low-power multiple-valued current-mode integrated circuit with current-source control and its application., , and . ASP-DAC, page 413-418. IEEE, (1997)Interconnection-Free Biomolecular Computing., , and . Computer, 25 (11): 41-50 (1992)Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 619-630 (2015)Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects., , and . J. Robotics Mechatronics, 8 (6): 501-507 (1996)Latency Minimization of Parallel VLSI Processors for Robotics Using Integer Programming., and . J. Robotics Mechatronics, 6 (2): 143-149 (1994)VLSI Computer for Robotics., and . J. Robotics Mechatronics, 1 (1): 68-73 (1989)Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure., and . J. Robotics Mechatronics, 8 (6): 516-523 (1996)Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic., , and . J. Multiple Valued Log. Soft Comput., 11 (5-6): 619-632 (2005)