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Leakage energy reduction techniques in deep submicron cache memories: a comparative study., , , and . ISCAS, IEEE, (2006)A high-speed energy-efficient 64-bit reconfigurable binary adder., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 939-943 (2003)Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3133-3137 (2015)Novel Varactor-Loaded Phasing Line for Reflectarray Unit Cell with Large Reconfigurability Frequency Range., , , , and . WorldCIST (2), volume 354 of Advances in Intelligent Systems and Computing, page 3-9. Springer, (2015)Design of Leading Zero Counters on FPGAs., , , and . IEEE Embed. Syst. Lett., 15 (3): 149-152 (September 2023)Power/throughput/area efficient PIM-based reconfigurable array for parallel processing., , , and . SoCC, page 375-378. IEEE, (2008)Multibit Full Comparator Logic in Quantum-Dot Cellular Automata., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (11): 4508-4512 (2022)Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (11): 3456-3460 (2021)Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip., , , and . J. Imaging, 6 (9): 85 (2020)Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes., , , , and . Sensors, 22 (8): 2839 (2022)