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A 28nm 1.07TFLOPS/mm2 Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing.

, , , , , , , and . CICC, page 1-2. IEEE, (2023)

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A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design., , , and . ISQED, page 191-197. IEEE, (2010)TSV-aware topology generation for 3D Clock Tree Synthesis., , , , , , and . ISQED, page 300-307. IEEE, (2013)A Novel Reconfigurable Computing Architecture for Image Signal Processing Using Circuit-Switched NoC and Synchronous Dataflow Model., , , and . CoRR, (2013)A Survey of FPGA Based Neural Network Accelerator., , , , and . CoRR, (2017)Increasing Compression Ratio of Low Complexity Compressive Sensing Video Encoder with Application-Aware Configurable Mechanism., , , and . CoRR, (2013)Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system., , , , and . DAC, page 13:1-13:6. ACM, (2015)Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits., , , , and . ISLPED, page 238-243. ACM, (2006)Nonparametric Topic Modeling with Neural Inference., , , , , and . CoRR, (2018)Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory., , , , , , and . ASP-DAC, page 407-413. IEEE, (2020)Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (2): 173-186 (2016)