Author of the publication

Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates.

, , , and . ISQED, page 242-247. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

65NM sub-threshold 11T-SRAM for ultra low voltage applications., , , , and . SoCC, page 113-118. IEEE, (2008)Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits., , , and . SoCC, page 259-264. IEEE, (2016)Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology., , , , , , , and . Microelectron. J., 45 (1): 23-34 (2014)Impact of NBTI on performance of domino logic circuits in nano-scale CMOS., , , and . Microelectron. J., 42 (12): 1327-1334 (2011)Postsilicon Adaptation for Low-Power SRAM under Process Variation., , , , and . IEEE Des. Test Comput., 27 (6): 26-35 (2010)Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies., and . SoCC, page 261-264. IEEE, (2006)Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS., and . ISQED, page 342-346. IEEE, (2012)A low-power SRAM using bit-line charge-recycling technique., , and . ISLPED, page 177-182. ACM, (2007)Low-overhead design technique for calibration of maximum frequency at multiple operating points., , , and . ICCAD, page 401-404. IEEE Computer Society, (2007)On Custom LUT-based Obfuscation., , , , , and . ACM Great Lakes Symposium on VLSI, page 477-482. ACM, (2019)