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Disambiguation of "Wong, Martin D. F."

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Information dispersion for trojan defense through high-level synthesis.

, , and . DAC, page 87:1-87:6. ACM, (2016)

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Alexander D F Lahmann

Blaise F D Bourgeois

Walter Wong

Martin F Almstetter

Martin F Polaschek

 

Other publications of authors with the same name

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation., , , and . VLSI Design, 15 (3): 587-594 (2002)Two-layer bus routing for high-speed printed circuit boards., and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 213-227 (2006)Accelerating aerial image simulation using improved CPU/GPU collaborative computing., , , , and . Comput. Electr. Eng., (2015)Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (7): 1256-1269 (2007)Matching-based algorithm for FPGA channel segmentation design., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (6): 784-791 (2001)NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (9): 1356-1365 (2012)Floorplan Design for Multimillion Gate FPGAs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2795-2805 (2006)An ECO routing algorithm for eliminating coupling-capacitance violations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1754-1762 (2006)Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 84-95 (2008)Minimum replication min-cut partitioning., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (10): 1221-1227 (1997)