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A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

S. Haas, T. Seifert, B. Nöthen, S. Scholze, S. Höppner, A. Dixius, E. Adeva, T. Augustin, F. Pauls, S. Moriam, M. Hasler, E. Fischer, Y. Chen, E. Matús, G. Ellguth, S. Hartmann, S. Schiefer, L. Cederström, D. Walter, S. Henker, S. Hänzsche, J. Uhlig, H. Eisenreich, S. Weithoffer, N. Wehn, R. Schüffny, C. Mayr, and G. Fettweis. DAC, page 47:1-47:6. ACM, (2017)

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Horst Eisenreich

Eisenreich Wolfgang

Rochus Eisenreich

Franz Eisenreich

Rochus Eisenreich

Other publications of authors with the same name

IC Design & Technology Co-Development: e-NVM & mmWave enablement of 22FDX™ Technology.S. Kolodinski, H. Eisenreich, S. Lehmann, and J. Müller. ICICDT, page 1-4. IEEE, (2021)Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology.S. Höppner, H. Eisenreich, D. Walter, A. Scharfe, A. Oefelein, F. Schraut, J. Schreiter, T. Riedel, H. Bauer, R. Niebsch and 7 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 2159-2163 (2020)Low power design of the X-GOLD® SDR 20 baseband processor.W. Raab, J. Berthold, J. Hachmann, D. Langen, M. Schreiner, H. Eisenreich, J. Schluessler, and G. Ellguth. DATE, page 792-793. IEEE Computer Society, (2010)A novel ADPLL design using successive approximation frequency control.H. Eisenreich, C. Mayr, S. Henker, M. Wickert, and R. Schüffny. Microelectron. J., 40 (11): 1613-1622 (2009)Efficient compensation of delay variations in high-speed network-on-chip data links.S. Höppner, D. Walter, H. Eisenreich, and R. Schüffny. SoC, page 55-58. IEEE, (2010)A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM.D. Walter, A. Scharfe, A. Oefelein, F. Schraut, H. Bauer, F. Csaszar, R. Niebsch, J. Schreiter, H. Eisenreich, and S. Höppner. COOL CHIPS, page 1-3. IEEE, (2020)10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.B. Noethen, O. Arnold, E. Adeva, T. Seifert, E. Fischer, S. Kunze, E. Matús, G. Fettweis, H. Eisenreich, G. Ellguth and 7 other author(s). ISSCC, page 188-189. IEEE, (2014)A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology.F. Schraut, H. Eisenreich, S. Höppner, and C. Mayr. ISCAS, page 1-5. IEEE, (2019)A power management architecture for fast per-core DVFS in heterogeneous MPSoCs.S. Höppner, C. Shao, H. Eisenreich, G. Ellguth, M. Ander, and R. Schüffny. ISCAS, page 261-264. IEEE, (2012)How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC.S. Höppner, J. Schreiter, R. Niebsch, S. Scherzer, U. Hensel, J. Winkler, M. Orgis, H. Eisenreich, D. Walter, U. Steeb and 6 other author(s). ESSDERC, page 66-69. IEEE, (2019)

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Disambiguation of "Eisenreich, Holger"

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A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

Please choose a person to relate this publication to

Horst Eisenreich

Eisenreich Wolfgang

Rochus Eisenreich

Franz Eisenreich

Rochus Eisenreich

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Eisenreich, Holger"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

Please choose a person to relate this publication to

Horst Eisenreich

Eisenreich Wolfgang

Rochus Eisenreich

Franz Eisenreich

Rochus Eisenreich

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
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A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.