( en | de | ru )

 

Disambiguation of "Ellguth, Georg"

Author of the publication

copydeleteadd this publication to your clipboard
10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.

, , , , , , , , , , , , , , , , and . ISSCC, page 188-189. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Peter Ellguth IAB Nürnberg

Martin Ellguth

Jennifer Sara Ellguth

Marwan Georges

Sotirios Georganas

 

Other publications of authors with the same name

Low power design of the X-GOLD® SDR 20 baseband processor., , , , , , , and . DATE, page 792-793. IEEE Computer Society, (2010)A low-power cell-based-design multi-port register file in 65nm CMOS technology., , , and . ISCAS, page 313-316. IEEE, (2010)Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS., , , , , , , , and . VLSI-SoC, page 155-158. IEEE, (2019)Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 9 other author(s). ISCAS, page 1-4. IEEE, (2017)Hardware Implementation of an OPC UA Server for Industrial Field Devices., , , , , , , , , and 6 other author(s). CoRR, (2021)Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 10 other author(s). ISCAS, page 1. IEEE, (2017)A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (11): 835-839 (2014)A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI., , , , , , , , , and 3 other author(s). IEEE Trans. Biomed. Circuits Syst., 16 (1): 94-107 (2022)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2973-2986 (2019)10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 188-189. IEEE, (2014)