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A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.

Y. Lin, Y. Wang, X. Hu, J. Feng, G. Wen, X. Xiong, H. Tian, and Y. Xie. ASICON, page 1-4. IEEE, (2021)

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Yufeng Huang

Yufeng Su

Yufeng Guo

Yufeng Kou

Yufeng Wan

Other publications of authors with the same name

An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication.X. Hu, Y. Wang, Z. Ma, G. Wen, Z. Wang, Z. Lu, Y. Liu, Y. Li, X. Liang, X. Zeng and 1 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 70 (11): 4216-4220 (November 2023)TransFoxMol: predicting molecular property with focused attention.J. Gao, Z. Shen, Y. Xie, J. Lu, Y. Lu, S. Chen, Q. Bian, Y. Guo, L. Shen, J. Wu and 5 other author(s). Briefings Bioinform., (September 2023)A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell.J. Zhang, Y. Ding, X. Xue, G. Jin, Y. Wu, Y. Xie, and Y. Lin. IEICE Trans. Electron., 93-C (12): 1692-1699 (2010)A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation.Z. Ma, X. Hu, Y. Wang, G. Wen, X. Zeng, and Y. Xie. ISCAS, page 1-5. IEEE, (2023)Weighted Failure Probability Calculation of Overhead Distribution Line in Random Wind Field.Z. Zhang, H. Hou, M. Li, Y. Xie, L. Zhu, and Y. Huang. SSCI, page 968-975. IEEE, (2020)A BIST scheme for high-speed Gain Cell eDRAM.B. Yan, Y. Xie, R. Yuan, and Y. Lin. ASICON, page 244-247. IEEE, (2011)Video co-segmentation based on directed graph.Y. Xie, Z. Liu, X. Zhou, W. Liu, and X. Zou. Multim. Tools Appl., 78 (8): 10353-10372 (2019)Multi-task Learning Model based on Multiple Characteristics and Multiple Interests for CTR prediction.Y. Xie, M. Li, K. Lu, S. Shah, and X. Zheng. DSC, page 1-7. IEEE, (2022)GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications.Z. Ma, X. Hu, G. Wen, Y. Wang, Z. Wang, Y. Lin, Y. Wang, Y. Guo, Y. Li, X. Liang and 2 other author(s). A-SSCC, page 1-3. IEEE, (2023)A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.Y. Lin, Y. Wang, X. Hu, J. Feng, G. Wen, X. Xiong, H. Tian, and Y. Xie. ASICON, page 1-4. IEEE, (2021)

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Disambiguation of "Xie, Yufeng"

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A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.

Please choose a person to relate this publication to

Yufeng Huang

Yufeng Su

Yufeng Guo

Yufeng Kou

Yufeng Wan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xie, Yufeng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.

Please choose a person to relate this publication to

Yufeng Huang

Yufeng Su

Yufeng Guo

Yufeng Kou

Yufeng Wan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.