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Parametrisable digital design of a sphere decoder with high-level synthesis., , , and . EUSIPCO, page 1349-1353. IEEE, (2017)Degradation and temperature analysis of voltage-controlled ring oscillators for robust and reliable oscillator designs in a 65nm bulk CMOS process., , , , and . MIXDES, page 353-358. IEEE, (2016)Optimum Operating Points of Transistors with minimal Aging-Aware Sensitivity., , , and . SBCCI, page 14:1-14:7. ACM, (2015)Behavioral modeling of a sensor interface circuit including various non-idealities., , , , and . SMACD, page 1-4. IEEE, (2017)Fast digital design space exploration with high-level synthesis: A case study with approximate conjugate gradient pursuit., , , , and . ACSSC, page 412-416. IEEE, (2016)NBTI and HCD aware behavioral models for reliability analysis of analog CMOS circuits., , , and . IRPS, page 1. IEEE, (2015)Rapid digital architecture design of orthogonal matching pursuit., , , , and . EUSIPCO, page 1857-1861. IEEE, (2016)An aging-aware transistor sizing tool regarding BTI and HCD degradation modes., , , , and . MIXDES, page 272-277. IEEE, (2015)Modeling of an analog recording system design for ECoG and AP signals., , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Variability-aware aging modeling for reliability analysis of an analog neural measurement system., , , and . ETS, page 1-6. IEEE, (2015)