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Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection.

, , , , , and . CICC, page 491-494. IEEE, (2002)

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Short channel models and scaling limits of SOI and bulk MOSFETs., , , and . IEEE J. Solid State Circuits, 29 (2): 122-125 (February 1994)Gigascale integration (GSI) technology.. SC, page 534-538. ACM, (1991)Modeling technology impact on cluster microprocessor performance., , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 909-920 (2003)Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection., , , , , and . CICC, page 491-494. IEEE, (2002)IntSim: A CAD tool for optimization of multilevel interconnect networks., , , , and . ICCAD, page 560-567. IEEE Computer Society, (2007)A compact physical via blockage model., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (6): 689-692 (2000)Relative inductance extraction method., and . CICC, page 481-484. IEEE, (2004)Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems., , and . CICC, page 421-428. IEEE, (2007)Nanoelectronics in retrospect, prospect and principle., , , and . ISSCC, page 31-35. IEEE, (2010)Exploring Microprocessor Architectures for Gigascale Integration., , , , , and . ARVLSI, page 242-255. IEEE Computer Society, (1999)