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Disambiguation of "Shan, Lei"

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SiGe BiCMOS integrated circuits for high-speed serial communication links.

, , , , , , , , , , , and . IBM J. Res. Dev., 47 (2-3): 259-282 (2003)

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Lei Lei

Lei Lei

Shan-Shan Zhan

Jiening Shan

Yunsheng Shan

 

Other publications of authors with the same name

Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture., , , , and . NCCET, volume 666 of Communications in Computer and Information Science, page 168-176. Springer, (2016)SiGe BiCMOS integrated circuits for high-speed serial communication links., , , , , , , , , and 2 other author(s). IBM J. Res. Dev., 47 (2-3): 259-282 (2003)GI/Geom/1 queue based on communication model for mesh networks., , , , , , and . Int. J. Commun. Syst., 27 (11): 3013-3029 (2014)A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 41 (12): 2885-2900 (2006)Improving graph collaborative filtering with multimodal-side-information-enriched contrastive learning., , , , , , and . J. Intell. Inf. Syst., 62 (1): 143-161 (February 2024)Indexing continuously changing data with mean-variance tree., , , , and . SAC, page 1125-1132. ACM, (2005)A Dynamic Multi-precision Fixed-Point Data Quantization Strategy for Convolutional Neural Network., , , and . NCCET, volume 666 of Communications in Computer and Information Science, page 102-111. Springer, (2016)A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 50 (8): 1917-1931 (2015)Indexing continuously changing data with mean-variance tree., , , , and . Int. J. High Perform. Comput. Netw., 5 (4): 263-272 (2008)A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology., , , , , , , , , and 6 other author(s). CICC, page 1-4. IEEE, (2014)